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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [cache/] [dcache_model.h] - Rev 1765

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1765 root 5766d 02h /or1k/branches/stable_0_2_x/or1ksim/cache/dcache_model.h
1646 This commit was manufactured by cvs2svn to create branch 'stable_0_2_x'. 6913d 05h /or1k/branches/stable_0_2_x/or1ksim/cache/dcache_model.h
1486 * Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity.		 nogj 7158d 14h /or1k/branches/stable_0_2_x/or1ksim/cache/dcache_model.h
1402 Do what dc_clock() did in mtspr() and remove it nogj 7206d 09h /or1k/branches/stable_0_2_x/or1ksim/cache/dcache_model.h
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7221d 13h /or1k/branches/stable_0_2_x/or1ksim/cache/dcache_model.h
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7256d 07h /or1k/branches/stable_0_2_x/or1ksim/cache/dcache_model.h
1308 Gyorgy Jeney: extensive cleanup phoenix 7461d 02h /or1k/branches/stable_0_2_x/or1ksim/cache/dcache_model.h
631 Real cache access is simulated now. simons 8363d 03h /or1k/branches/stable_0_2_x/or1ksim/cache/dcache_model.h
626 store buffer added markom 8363d 16h /or1k/branches/stable_0_2_x/or1ksim/cache/dcache_model.h
428 cache configuration added markom 8412d 10h /or1k/branches/stable_0_2_x/or1ksim/cache/dcache_model.h
5 Data and instruction cache simulation added. lampret 9061d 03h /or1k/branches/stable_0_2_x/or1ksim/cache/dcache_model.h

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