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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [mmu/] [dmmu.h] - Rev 1778

Rev	Log message	Author	Age	Path
1765		root	5730d 15h	/or1k/branches/stable_0_2_x/or1ksim/mmu/dmmu.h
1646	This commit was manufactured by cvs2svn to create branch 'stable_0_2_x'.		6877d 18h	/or1k/branches/stable_0_2_x/or1ksim/mmu/dmmu.h
1539	Speed up the dmmu	nogj	7075d 07h	/or1k/branches/stable_0_2_x/or1ksim/mmu/dmmu.h
1350	Mark a simulated cpu address as such, by introducing the new oraddr_t type	nogj	7220d 20h	/or1k/branches/stable_0_2_x/or1ksim/mmu/dmmu.h
1308	Gyorgy Jeney: extensive cleanup	phoenix	7425d 15h	/or1k/branches/stable_0_2_x/or1ksim/mmu/dmmu.h
430	dpfault and ipfault exceptions implemented	markom	8376d 23h	/or1k/branches/stable_0_2_x/or1ksim/mmu/dmmu.h
425	immu and dmmu configurations added	markom	8377d 01h	/or1k/branches/stable_0_2_x/or1ksim/mmu/dmmu.h
204	Added function prototypes to stop gcc from complaining	erez	8459d 01h	/or1k/branches/stable_0_2_x/or1ksim/mmu/dmmu.h
62	OR1K DMMU model.	lampret	8803d 06h	/or1k/branches/stable_0_2_x/or1ksim/mmu/dmmu.h
6	Just a regular update with exception of cache simulation. MMU simulation still under development.	lampret	9025d 16h	/or1k/branches/stable_0_2_x/or1ksim/mmu/dmmu.h