OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [peripheral/] [mc.c] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5765d 12h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
1646 This commit was manufactured by cvs2svn to create branch 'stable_0_2_x'. 6912d 15h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
1557 Fix most warnings issued by gcc4 nogj 7048d 02h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
1519 Add a usefull trace to the mc nogj 7114d 23h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
1490 Make the mc peripheral use the new debugging functions nogj 7153d 02h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
1486 * Seporate out the code used for handling the memory peripheral to peripheral/memory.c
* Mostly decouple the memory controller from the internals of the memory handling.
* Rewrite memory handling to be more linear and thus much faster.
* Issue a bus error on read/write with invalid granularity.		 nogj 7157d 23h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
1461 Add an optional `enabled' paramter to every peripheral nogj 7205d 18h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
1373 Cleanup the memory controller useing the new callbacks nogj 7246d 13h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
1359 Pass private data in readfunc/writefunc callbacks nogj 7246d 13h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7246d 14h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7255d 17h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7460d 11h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
997 PRINTF should be used instead of printf; command redirection repaired markom 8157d 02h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
970 Testbench is now running on ORP architecture platform. simons 8164d 13h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
804 memory regions can now overlap with MC -- not according to MC spec markom 8292d 21h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
742 Added status info dump. ivang 8317d 23h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
545 Fixed mc_read_word() bug! ivang 8383d 17h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
543 Memory controller fixed. simons 8383d 20h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
539 Missing parts added. simons 8384d 00h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8438d 23h /or1k/branches/stable_0_2_x/or1ksim/peripheral/mc.c

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.