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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [testbench/] [cache.c] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5765d 11h	/or1k/branches/stable_0_2_x/or1ksim/testbench/cache.c
1646	This commit was manufactured by cvs2svn to create branch 'stable_0_2_x'.		6912d 14h	/or1k/branches/stable_0_2_x/or1ksim/testbench/cache.c
631	Real cache access is simulated now.	simons	8362d 12h	/or1k/branches/stable_0_2_x/or1ksim/testbench/cache.c
621	Cache test works on hardware.	simons	8363d 23h	/or1k/branches/stable_0_2_x/or1ksim/testbench/cache.c
575	Not needed to be compiled with -O2 optimization any more.	simons	8376d 22h	/or1k/branches/stable_0_2_x/or1ksim/testbench/cache.c
574	fixed some tests to work	markom	8377d 00h	/or1k/branches/stable_0_2_x/or1ksim/testbench/cache.c
534	Changed to work with new simulator.	simons	8384d 21h	/or1k/branches/stable_0_2_x/or1ksim/testbench/cache.c
484	Changed to support execution from various addresses.	simons	8403d 14h	/or1k/branches/stable_0_2_x/or1ksim/testbench/cache.c
424	memory configuration file joined into .cfg file; *mem.cfg are obsolete; read-only and write-only memory is supported; memory logging is not yet supported; update of testbench - only cache test fails, since it writes to RO memory	markom	8411d 23h	/or1k/branches/stable_0_2_x/or1ksim/testbench/cache.c
349	Some bugs regarding cache simulation fixed.	simons	8436d 14h	/or1k/branches/stable_0_2_x/or1ksim/testbench/cache.c
322	IC test repaired.C	simons	8442d 16h	/or1k/branches/stable_0_2_x/or1ksim/testbench/cache.c
224	added various tests	markom	8459d 22h	/or1k/branches/stable_0_2_x/or1ksim/testbench/cache.c