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[/] [or1k/] [branches/] [stable_0_2_x/] [or1ksim/] [testbench/] [int_test.S] - Rev 1765

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1765 root 5765d 11h /or1k/branches/stable_0_2_x/or1ksim/testbench/int_test.S
1646 This commit was manufactured by cvs2svn to create branch 'stable_0_2_x'. 6912d 14h /or1k/branches/stable_0_2_x/or1ksim/testbench/int_test.S
970 Testbench is now running on ORP architecture platform. simons 8164d 12h /or1k/branches/stable_0_2_x/or1ksim/testbench/int_test.S
956 Changed to work with or32-uclinux tool chain. Everything works except keyboard test. simons 8166d 18h /or1k/branches/stable_0_2_x/or1ksim/testbench/int_test.S
802 Cache and tick timer tests fixed. simons 8297d 00h /or1k/branches/stable_0_2_x/or1ksim/testbench/int_test.S
619 all test pass, after newest changes markom 8363d 23h /or1k/branches/stable_0_2_x/or1ksim/testbench/int_test.S
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8372d 11h /or1k/branches/stable_0_2_x/or1ksim/testbench/int_test.S
576 some risc test added markom 8376d 19h /or1k/branches/stable_0_2_x/or1ksim/testbench/int_test.S

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