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[/] [or1k/] [tags/] [nog_patch_50/] [or1ksim/] [cache/] [dcache_model.h] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5587d 08h	/or1k/tags/nog_patch_50/or1ksim/cache/dcache_model.h
1425	This commit was manufactured by cvs2svn to create tag 'nog_patch_50'.		7027d 15h	/or1k/tags/nog_patch_50/or1ksim/cache/dcache_model.h
1402	Do what dc_clock() did in mtspr() and remove it	nogj	7027d 15h	/or1k/tags/nog_patch_50/or1ksim/cache/dcache_model.h
1382	Nir Mor: Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.	nogj	7042d 19h	/or1k/tags/nog_patch_50/or1ksim/cache/dcache_model.h
1350	Mark a simulated cpu address as such, by introducing the new oraddr_t type	nogj	7077d 13h	/or1k/tags/nog_patch_50/or1ksim/cache/dcache_model.h
1308	Gyorgy Jeney: extensive cleanup	phoenix	7282d 08h	/or1k/tags/nog_patch_50/or1ksim/cache/dcache_model.h
631	Real cache access is simulated now.	simons	8184d 09h	/or1k/tags/nog_patch_50/or1ksim/cache/dcache_model.h
626	store buffer added	markom	8184d 22h	/or1k/tags/nog_patch_50/or1ksim/cache/dcache_model.h
428	cache configuration added	markom	8233d 16h	/or1k/tags/nog_patch_50/or1ksim/cache/dcache_model.h
5	Data and instruction cache simulation added.	lampret	8882d 09h	/or1k/tags/nog_patch_50/or1ksim/cache/dcache_model.h