OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_50/] [or1ksim/] [cache/] [icache_model.h] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5595d 20h /or1k/tags/nog_patch_50/or1ksim/cache/icache_model.h
1425 This commit was manufactured by cvs2svn to create tag 'nog_patch_50'. 7036d 03h /or1k/tags/nog_patch_50/or1ksim/cache/icache_model.h
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7036d 03h /or1k/tags/nog_patch_50/or1ksim/cache/icache_model.h
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.
nogj 7051d 07h /or1k/tags/nog_patch_50/or1ksim/cache/icache_model.h
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7086d 01h /or1k/tags/nog_patch_50/or1ksim/cache/icache_model.h
1308 Gyorgy Jeney: extensive cleanup phoenix 7290d 20h /or1k/tags/nog_patch_50/or1ksim/cache/icache_model.h
631 Real cache access is simulated now. simons 8192d 21h /or1k/tags/nog_patch_50/or1ksim/cache/icache_model.h
429 cache configuration added markom 8242d 04h /or1k/tags/nog_patch_50/or1ksim/cache/icache_model.h
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8449d 14h /or1k/tags/nog_patch_50/or1ksim/cache/icache_model.h
76 regular update lampret 8649d 11h /or1k/tags/nog_patch_50/or1ksim/cache/icache_model.h
5 Data and instruction cache simulation added. lampret 8890d 21h /or1k/tags/nog_patch_50/or1ksim/cache/icache_model.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.