OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [nog_patch_50/] [or1ksim/] [cpu/] [common/] [abstract.c] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5623d 11h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1425 This commit was manufactured by cvs2svn to create tag 'nog_patch_50'. 7063d 18h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1386 Rework exception handling nogj 7069d 22h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1375 Remove FAST_SIM, it nolonger provides a speed up nogj 7104d 13h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1362 initialise dev_mem->chip_select in register_memory nogj 7104d 13h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1359 Pass private data in readfunc/writefunc callbacks nogj 7104d 13h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7104d 13h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1354 typing fixes phoenix 7112d 19h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7113d 16h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7126d 20h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1324 memory access functions fixes phoenix 7224d 11h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1319 cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. phoenix 7230d 11h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7318d 11h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1244 Added "cm" command to copy data inside memory.
Make or1ksim work on little endian platforms.
Port to Mac OS X.
Some bugfixes.
Allow JTAG write access to read-only memory regions.		 hpanther 7485d 19h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1240 additional functions to bypass cache and mmu needed for peripheral devices phoenix 7490d 06h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
1218 segfault when there is no memory context fix phoenix 7538d 08h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
997 PRINTF should be used instead of printf; command redirection repaired markom 8015d 01h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
992 A bug when cache enabled and bus error comes fixed. simons 8016d 17h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
970 Testbench is now running on ORP architecture platform. simons 8022d 12h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c
897 improved CUC GUI; pre/unroll bugs fixed markom 8051d 17h /or1k/tags/nog_patch_50/or1ksim/cpu/common/abstract.c

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.