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[/] [or1k/] [tags/] [nog_patch_68/] [or1ksim/] [cache/] [icache_model.c] - Rev 1782

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1765 root 5586d 00h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
1462 This commit was manufactured by cvs2svn to create tag 'nog_patch_68'. 7026d 07h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7026d 07h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
1406 Fix the declaration of `sec' in reg_ic_sec nogj 7026d 07h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
1404 Move the function of ic_clock() to mtspr() and remove it nogj 7026d 07h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
1386 Rework exception handling nogj 7032d 11h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7041d 11h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7067d 02h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7076d 05h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7089d 09h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7281d 00h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
1085 Bug fixed. simons 7888d 01h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
997 PRINTF should be used instead of printf; command redirection repaired markom 7977d 14h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
992 A bug when cache enabled and bus error comes fixed. simons 7979d 06h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
884 code cleaning - a lot of global variables moved to runtime struct markom 8021d 12h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
638 TLBTR CI bit is now working properly. simons 8180d 02h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
631 Real cache access is simulated now. simons 8183d 01h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8204d 10h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
429 cache configuration added markom 8232d 08h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c
428 cache configuration added markom 8232d 08h /or1k/tags/nog_patch_68/or1ksim/cache/icache_model.c

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