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[/] [or1k/] [tags/] [nog_patch_70/] [or1ksim/] [cache/] [dcache_model.c] - Rev 1765

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1765 root 5563d 13h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
1466 This commit was manufactured by cvs2svn to create tag 'nog_patch_70'. 7003d 19h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7003d 20h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
1402 Do what dc_clock() did in mtspr() and remove it nogj 7003d 20h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
1386 Rework exception handling nogj 7009d 23h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
1382 Nir Mor:
Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.		 nogj 7018d 23h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7044d 15h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7053d 18h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7066d 22h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7258d 12h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
1085 Bug fixed. simons 7865d 14h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
997 PRINTF should be used instead of printf; command redirection repaired markom 7955d 03h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
992 A bug when cache enabled and bus error comes fixed. simons 7956d 18h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
884 code cleaning - a lot of global variables moved to runtime struct markom 7999d 01h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
638 TLBTR CI bit is now working properly. simons 8157d 14h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
631 Real cache access is simulated now. simons 8160d 13h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8181d 22h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
428 cache configuration added markom 8209d 21h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
261 modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc markom 8249d 01h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed		 markom 8334d 21h /or1k/tags/nog_patch_70/or1ksim/cache/dcache_model.c

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