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[/] [or1k/] [tags/] [nog_patch_73/] [or1ksim/] [cache/] [dcache_model.h] - Rev 1780

Rev	Log message	Author	Age	Path
1765		root	5588d 13h	/or1k/tags/nog_patch_73/or1ksim/cache/dcache_model.h
1472	This commit was manufactured by cvs2svn to create tag 'nog_patch_73'.		7028d 19h	/or1k/tags/nog_patch_73/or1ksim/cache/dcache_model.h
1402	Do what dc_clock() did in mtspr() and remove it	nogj	7028d 20h	/or1k/tags/nog_patch_73/or1ksim/cache/dcache_model.h
1382	Nir Mor: Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.	nogj	7043d 23h	/or1k/tags/nog_patch_73/or1ksim/cache/dcache_model.h
1350	Mark a simulated cpu address as such, by introducing the new oraddr_t type	nogj	7078d 18h	/or1k/tags/nog_patch_73/or1ksim/cache/dcache_model.h
1308	Gyorgy Jeney: extensive cleanup	phoenix	7283d 12h	/or1k/tags/nog_patch_73/or1ksim/cache/dcache_model.h
631	Real cache access is simulated now.	simons	8185d 13h	/or1k/tags/nog_patch_73/or1ksim/cache/dcache_model.h
626	store buffer added	markom	8186d 02h	/or1k/tags/nog_patch_73/or1ksim/cache/dcache_model.h
428	cache configuration added	markom	8234d 21h	/or1k/tags/nog_patch_73/or1ksim/cache/dcache_model.h
5	Data and instruction cache simulation added.	lampret	8883d 14h	/or1k/tags/nog_patch_73/or1ksim/cache/dcache_model.h