OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [testbench/] [except_test_s.S] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5563d 13h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/except_test_s.S
1753 This commit was manufactured by cvs2svn to create tag 'rel-0-3-0-rc2'. 5682d 20h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/except_test_s.S
970 Testbench is now running on ORP architecture platform. simons 7962d 14h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/except_test_s.S
956 Changed to work with or32-uclinux tool chain. Everything works except keyboard test. simons 7964d 19h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/except_test_s.S
608 Range exception removed from test. simons 8167d 23h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/except_test_s.S
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8170d 13h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/except_test_s.S
522 Bug fixed. simons 8184d 18h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/except_test_s.S
519 except_test.S renamed to except_test_s.S simons 8184d 21h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/except_test_s.S

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.