OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel-0-3-0-rc2/] [or1ksim/] [testbench/] [mmu.c] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5563d 14h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
1753 This commit was manufactured by cvs2svn to create tag 'rel-0-3-0-rc2'. 5682d 21h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
1614 CI should not be set in dMMU translation tables or one gets different behaviour with dMMU on or off in case data cache is enabled. care should be taken for addresses higher than 0x7fff_ffff where the situation is just reversed. (since or1200 does not cache upper half of address space if there is no dMMU) phoenix 6755d 12h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
1446 Cosmetic fixes nogj 7003d 20h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
1024 Mess with printf/PRINTF fixed. Ethernet test changed to support latest changes. simons 7943d 01h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
997 PRINTF should be used instead of printf; command redirection repaired markom 7955d 04h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
970 Testbench is now running on ORP architecture platform. simons 7962d 15h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
957 Flash at 0x04000000 RAM at 0x00000000. Only MMU test works. simons 7964d 16h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
639 MMU cache inhibit bit test added. simons 8157d 15h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8170d 13h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
509 unused var warning corrected markom 8186d 23h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
480 RTL_SIM define added for shorter simulation runtime. simons 8201d 22h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
466 EEAR is used for determing ITLB miss and IPF page address. simons 8202d 14h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
457 Page size set to 8192. simons 8206d 17h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
448 Permission test added. simons 8208d 03h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
417 ITLB test tested on simulator. simons 8212d 12h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
415 DTLB test tested on simulator. simons 8213d 13h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
413 some section changes markom 8213d 23h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
412 *** empty log message *** simons 8214d 00h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c
410 MMU test added. simons 8214d 20h /or1k/tags/rel-0-3-0-rc2/or1ksim/testbench/mmu.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.