| Rev |
Log message |
Author |
Age |
Path |
| 1765 |
|
root |
5612d 15h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1758 |
This commit was manufactured by cvs2svn to create tag 'rel-0-3-0-rc3'. |
|
5626d 20h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1751 |
These are the changes to support Or1ksim 0.3.0rc2. Most significantly they provide GDB RSP support. They also fix 5 outstanding bugs and satisfy one new feature request. |
jeremybennett |
5732d 00h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1748 |
These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes
are explained in the NEWS, README and ChangeLog files. A number of
long-standing bugs are fixed (see the OpenRISC tracker), and the code is
brought up to a consistent standard, following the GNU coding conventions
throughout.
Argument parsing now uses argtable2, and a User Guide has been added.
Documentation throughout has been extended to be compatible with Doxygen,
providing a further level of technical detail on the internals. |
jeremybennett |
5761d 20h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1692 |
Instead of playing games with the esp when a jump needs to be executed, use
longjmp() to get to the jump handling code. |
nogj |
6758d 17h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1686 |
Remove the immu_ex_from_insn hack. |
nogj |
6758d 17h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1678 |
Remove the ts_current hack by haveing the temporaries always shipped out before
any instruction that has the posibility to generate an exception |
nogj |
6758d 18h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1585 |
added missing exception, fixes segfault with trap exception |
phoenix |
6849d 16h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1525 |
Rename ADDR_PAGE to IADDR_PAGE |
nogj |
6962d 02h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1510 |
Create a seporate debug channel to dump exceptions to |
nogj |
6962d 02h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1508 |
Remove m{f,t}spr calls where we can access the spr directly |
nogj |
6962d 02h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1506 |
* Remove very slow {set,test}sprbit{,s} functions.
* Remove uses of getsprbits in time critical functions. |
nogj |
6962d 02h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1481 |
Remove the useless cross reference stuff: it was a bad idea to begin with |
nogj |
7025d 19h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1473 |
Add warning that except_handle may not return |
nogj |
7052d 22h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1452 |
Implement a dynamic recompiler to speed up the execution |
nogj |
7052d 22h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1442 |
Replace some problematic calles to mfspr/mtspr with direct access to the spr |
nogj |
7052d 22h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1432 |
Collect most of the cpu state variables in a structure (cpu_state) |
nogj |
7052d 22h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1386 |
Rework exception handling |
nogj |
7059d 02h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1350 |
Mark a simulated cpu address as such, by introducing the new oraddr_t type |
nogj |
7102d 20h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
| 1319 |
cpu/sim memory accesses separation, tick, exception, nr. of operands, cycles count,... corrections. |
phoenix |
7219d 15h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/except.c |
