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Author |
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1765 |
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root |
5646d 00h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
1758 |
This commit was manufactured by cvs2svn to create tag 'rel-0-3-0-rc3'. |
|
5660d 06h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
1748 |
These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes
are explained in the NEWS, README and ChangeLog files. A number of
long-standing bugs are fixed (see the OpenRISC tracker), and the code is
brought up to a consistent standard, following the GNU coding conventions
throughout.
Argument parsing now uses argtable2, and a User Guide has been added.
Documentation throughout has been extended to be compatible with Doxygen,
providing a further level of technical detail on the internals. |
jeremybennett |
5795d 06h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
1532 |
Add pretty spr dumping code |
nogj |
6994d 03h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
1508 |
Remove m{f,t}spr calls where we can access the spr directly |
nogj |
6995d 11h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
1506 |
* Remove very slow {set,test}sprbit{,s} functions.
* Remove uses of getsprbits in time critical functions. |
nogj |
6995d 11h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
1442 |
Replace some problematic calles to mfspr/mtspr with direct access to the spr |
nogj |
7086d 07h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
1432 |
Collect most of the cpu state variables in a structure (cpu_state) |
nogj |
7086d 07h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
1354 |
typing fixes |
phoenix |
7135d 08h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
1350 |
Mark a simulated cpu address as such, by introducing the new oraddr_t type |
nogj |
7136d 05h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
997 |
PRINTF should be used instead of printf; command redirection repaired |
markom |
8037d 14h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
728 |
tick timer works with scheduler |
markom |
8206d 12h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
644 |
Modified logging of SPR accesses. Logging only explicit instruction accesses. |
ivang |
8237d 09h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
624 |
Added logging of writes/read to/from SPR registers. |
ivang |
8244d 07h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
600 |
No more low/high priority interrupts (PICPR removed). Added tick timer exception. |
simons |
8253d 00h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
518 |
some more performance optimizations |
markom |
8268d 08h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
517 |
some performance optimizations |
markom |
8268d 09h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
479 |
connection with gdb repaired; temp_except_delay removed; lot of except and debug code cleaned; sys 203 causes stall under gdb; non-sim memory area log bug fixed |
markom |
8284d 09h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
167 |
- SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed |
markom |
8417d 09h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |
123 |
Bugs fixed:
- l.rfe temporarly disables exceptions
- l.sys does PC -= 4
- breakpoints now supported at peripheria locations
- uart0.rt/.tx nonexistent file segment fault
Other modifications:
- replaced string names to instruction indexes
- execute.c executes specified (in ISA table) function
- modified ISA table - flag needed for gdb
- added or32.c, which supports or32.h
- added new instructions l.mac, l.msb, l.maci, l.macrc
and their executing functions (opcodes to be revisited)
- added header acconfig.h
- modified configuration files |
markom |
8474d 09h |
/or1k/tags/rel-0-3-0-rc3/or1ksim/cpu/or1k/sprs.h |