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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Rev 1780

Rev	Log message	Author	Age	Path
1765		root	5587d 06h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_alu.v
896	This commit was manufactured by cvs2svn to create tag 'rel_1'.		8018d 06h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_alu.v
795	Added a directive to ignore signed division variables that are only used in simulation.	lampret	8125d 12h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_alu.v
794	Added again just recently removed full_case directive	lampret	8125d 12h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_alu.v
788	Some of the warnings fixed.	lampret	8125d 13h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_alu.v
617	Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.	lampret	8186d 03h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_alu.v
562	Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.	lampret	8199d 22h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_alu.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8210d 20h	/or1k/tags/rel_1/or1200/rtl/verilog/or1200_alu.v