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[/] [or1k/] [tags/] [rel_1/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1765

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1765 root 5602d 18h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
896 This commit was manufactured by cvs2svn to create tag 'rel_1'. 8033d 18h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8033d 18h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
870 Added defines for enabling generic FF based memory macro for register file. lampret 8070d 00h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8141d 00h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
788 Some of the warnings fixed. lampret 8141d 01h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8141d 21h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
776 Updated defines. lampret 8141d 21h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
737 Added alternative for critical path in DU. lampret 8156d 16h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8159d 15h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8187d 12h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
636 Fixed combinational loops. lampret 8196d 20h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8210d 02h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8211d 08h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
569 Default ASIC configuration does not sample WB inputs. lampret 8215d 07h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
536 Fixed typo. OR1200_REGISTERED_OUTPUTS was not defined. Should be. lampret 8221d 15h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
512 Uncommented OR1200_REGISTERED_OUTPUTS for FPGA target. lampret 8225d 19h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8226d 08h /or1k/tags/rel_1/or1200/rtl/verilog/or1200_defines.v

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