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[/] [or1k/] [tags/] [rel_13/] [or1200/] [rtl/] [verilog/] [or1200_spram_1024x8.v] - Rev 1772

Rev	Log message	Author	Age	Path
1765		root	5629d 13h	/or1k/tags/rel_13/or1200/rtl/verilog/or1200_spram_1024x8.v
1189	This commit was manufactured by cvs2svn to create tag 'rel_13'.		7652d 03h	/or1k/tags/rel_13/or1200/rtl/verilog/or1200_spram_1024x8.v
1184	Scan signals mess fixed.	simons	7659d 19h	/or1k/tags/rel_13/or1200/rtl/verilog/or1200_spram_1024x8.v
1179	BIST interface added for Artisan memory instances.	simons	7667d 22h	/or1k/tags/rel_13/or1200/rtl/verilog/or1200_spram_1024x8.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7794d 11h	/or1k/tags/rel_13/or1200/rtl/verilog/or1200_spram_1024x8.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7965d 16h	/or1k/tags/rel_13/or1200/rtl/verilog/or1200_spram_1024x8.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8253d 04h	/or1k/tags/rel_13/or1200/rtl/verilog/or1200_spram_1024x8.v