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[/] [or1k/] [tags/] [rel_15/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5586d 17h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_dpram_32x32.v
1201	This commit was manufactured by cvs2svn to create tag 'rel_15'.		7558d 08h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_dpram_32x32.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7751d 15h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_dpram_32x32.v
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8125d 21h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_dpram_32x32.v
636	Fixed combinational loops.	lampret	8180d 20h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_dpram_32x32.v
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8190d 08h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_dpram_32x32.v
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8194d 02h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_dpram_32x32.v
573	Fixed module name when compiling with OR1200_XILINX_RAM32X1D	lampret	8198d 10h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_dpram_32x32.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8210d 08h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_dpram_32x32.v