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[/] [or1k/] [tags/] [rel_15/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x8.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5589d 22h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_spram_2048x8.v
1201	This commit was manufactured by cvs2svn to create tag 'rel_15'.		7561d 13h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_spram_2048x8.v
1200	mbist signals updated according to newest convention	markom	7561d 13h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_spram_2048x8.v
1184	Scan signals mess fixed.	simons	7620d 04h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_spram_2048x8.v
1179	BIST interface added for Artisan memory instances.	simons	7628d 08h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_spram_2048x8.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7754d 20h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_spram_2048x8.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7926d 01h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_spram_2048x8.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8213d 13h	/or1k/tags/rel_15/or1200/rtl/verilog/or1200_spram_2048x8.v