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[/] [or1k/] [tags/] [rel_16/] [or1200/] [rtl/] [verilog/] [or1200_spram_2048x32.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5620d 09h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_2048x32.v
1212	This commit was manufactured by cvs2svn to create tag 'rel_16'.		7543d 08h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_2048x32.v
1200	mbist signals updated according to newest convention	markom	7592d 00h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_2048x32.v
1184	Scan signals mess fixed.	simons	7650d 15h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_2048x32.v
1179	BIST interface added for Artisan memory instances.	simons	7658d 18h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_2048x32.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7785d 07h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_2048x32.v
1077	Signal scanb_sen renamed to scanb_en.	mohor	7945d 17h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_2048x32.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7956d 12h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_2048x32.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8244d 00h	/or1k/tags/rel_16/or1200/rtl/verilog/or1200_spram_2048x32.v