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[/] [or1k/] [tags/] [rel_24/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1776

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1765 root 5620d 09h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1238 This commit was manufactured by cvs2svn to create tag 'rel_24'. 7498d 22h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1226 interface to debug changed; no more opselect; stb-ack protocol markom 7502d 01h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1225 Separate instruction and data QMEM decoders, QMEM acknowledge and byte-select added andreje 7505d 09h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1220 Exception prefix configuration changed. simons 7530d 18h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1207 Static exception prefix. lampret 7543d 08h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1171 Added embedded memory QMEM. lampret 7692d 16h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7725d 05h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1159 No functional changes. Added defines to disable implementation of multiplier/MAC lampret 7768d 08h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1155 No functional change. Only added customization for exception vectors. lampret 7771d 10h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7784d 11h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1132 RFRAM defines comments updated. Altera LPM option added. lampret 7785d 06h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7904d 23h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1078 Previous check-in was done by mistake. mohor 7945d 17h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1077 Signal scanb_sen renamed to scanb_en. mohor 7945d 17h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7956d 12h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1055 Removed obsolete comment. lampret 7988d 05h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7996d 02h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 7996d 13h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7997d 02h /or1k/tags/rel_24/or1200/rtl/verilog/or1200_defines.v

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