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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_alu.v] - Rev 1765

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1765 root 5584d 08h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v
1253 This commit was manufactured by cvs2svn to create tag 'rel_26'. 7439d 05h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7689d 04h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v
1159 No functional changes. Added defines to disable implementation of multiplier/MAC lampret 7732d 07h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7960d 01h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 7960d 12h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7961d 01h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 7964d 08h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v
795 Added a directive to ignore signed division variables that are only used in simulation. lampret 8122d 14h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v
794 Added again just recently removed full_case directive lampret 8122d 14h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v
788 Some of the warnings fixed. lampret 8122d 16h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8183d 06h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8197d 00h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8207d 23h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_alu.v

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