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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_cpu.v] - Rev 1765

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1765 root 5584d 09h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
1253 This commit was manufactured by cvs2svn to create tag 'rel_26'. 7439d 06h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
1252 preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. lampret 7439d 06h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
1214 Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. simons 7502d 20h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7689d 05h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7961d 02h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 7971d 06h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8015d 09h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
791 Fixed some ports in instnatiations that were removed from the modules lampret 8122d 15h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
788 Some of the warnings fixed. lampret 8122d 16h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8169d 03h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
636 Fixed combinational loops. lampret 8178d 11h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8183d 06h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
595 Fixed 'the NPC single-step fix'. lampret 8192d 17h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8193d 00h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8197d 01h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8207d 23h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_cpu.v

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