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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_immu_top.v] - Rev 1765

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1765 root 5584d 10h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
1253 This commit was manufactured by cvs2svn to create tag 'rel_26'. 7439d 07h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
1214 Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. simons 7502d 21h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
1171 Added embedded memory QMEM. lampret 7656d 17h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7689d 05h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
1161 When OR1200_NO_IMMU and OR1200_NO_IC are not both defined or undefined at the same time, results in a IC bug. Fixed. lampret 7689d 05h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7920d 12h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
1053 Disabled cache inhibit atttribute. lampret 7952d 05h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
977 Added store buffer. lampret 7980d 12h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 7985d 02h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
942 Delayed external access at page crossing. lampret 7987d 03h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
788 Some of the warnings fixed. lampret 8122d 17h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8169d 04h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
636 Fixed combinational loops. lampret 8178d 12h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8183d 07h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
562 Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if. lampret 8197d 02h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8208d 00h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_immu_top.v

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