OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_pic.v] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5584d 08h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_pic.v
1253 This commit was manufactured by cvs2svn to create tag 'rel_26'. 7439d 05h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_pic.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7689d 04h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_pic.v
788 Some of the warnings fixed. lampret 8122d 16h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_pic.v
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8192d 23h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_pic.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8207d 23h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_pic.v

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.