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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_top.v] - Rev 1765

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1765 root 5584d 08h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
1253 This commit was manufactured by cvs2svn to create tag 'rel_26'. 7439d 05h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
1252 preliminary HW breakpoints support in debug unit (by default disabled). To enable define OR1200_DU_HWBKPTS. lampret 7439d 05h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
1233 Errors fixed. simons 7463d 10h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
1231 Error fixed. simons 7463d 12h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
1229 Error fixed. simons 7463d 12h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
1226 interface to debug changed; no more opselect; stb-ack protocol markom 7466d 00h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
1214 Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed. simons 7502d 19h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
1209 Fixed instantiation name. lampret 7507d 07h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
1175 Added three missing wire declarations. No functional changes. lampret 7654d 06h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
1171 Added embedded memory QMEM. lampret 7656d 15h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
1163 This commit was manufactured by cvs2svn to create branch 'branch_qmem'. 7689d 04h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7868d 22h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 7920d 11h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
977 Added store buffer. lampret 7980d 11h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8015d 08h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
788 Some of the warnings fixed. lampret 8122d 15h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8169d 02h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
636 Fixed combinational loops. lampret 8178d 11h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8183d 05h /or1k/tags/rel_26/or1200/rtl/verilog/or1200_top.v

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