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[/] [or1k/] [tags/] [rel_26/] [or1200/] [rtl/] [verilog/] [or1200_wb_biu.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5584d 08h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_wb_biu.v
1253	This commit was manufactured by cvs2svn to create tag 'rel_26'.		7439d 06h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_wb_biu.v
1171	Added embedded memory QMEM.	lampret	7656d 16h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_wb_biu.v
1163	This commit was manufactured by cvs2svn to create branch 'branch_qmem'.		7689d 04h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_wb_biu.v
1140	Fixed OR1200_CLKDIV_x_SUPPORTED defines. Fixed order of ifdefs.	lampret	7748d 10h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_wb_biu.v
1104	Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional.	lampret	7868d 22h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_wb_biu.v
1054	Fixed a combinational loop.	lampret	7952d 04h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_wb_biu.v
943	Added optional retry counter for wb_rty_i. Added graceful termination for aborted transfers.	lampret	7987d 02h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_wb_biu.v
895	Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.	lampret	8015d 09h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_wb_biu.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8207d 23h	/or1k/tags/rel_26/or1200/rtl/verilog/or1200_wb_biu.v