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[/] [or1k/] [tags/] [rel_28/] [or1200/] [rtl/] [verilog/] [or1200_dc_tag.v] - Rev 1777

Rev	Log message	Author	Age	Path
1765		root	5664d 12h	/or1k/tags/rel_28/or1200/rtl/verilog/or1200_dc_tag.v
1294	This commit was manufactured by cvs2svn to create tag 'rel_28'.		7400d 16h	/or1k/tags/rel_28/or1200/rtl/verilog/or1200_dc_tag.v
1293	Non-functional changes. Coding style fixes.	lampret	7400d 16h	/or1k/tags/rel_28/or1200/rtl/verilog/or1200_dc_tag.v
1267	Merged branch_qmem into main tree.	lampret	7465d 02h	/or1k/tags/rel_28/or1200/rtl/verilog/or1200_dc_tag.v
1200	mbist signals updated according to newest convention	markom	7636d 03h	/or1k/tags/rel_28/or1200/rtl/verilog/or1200_dc_tag.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	8000d 15h	/or1k/tags/rel_28/or1200/rtl/verilog/or1200_dc_tag.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8288d 03h	/or1k/tags/rel_28/or1200/rtl/verilog/or1200_dc_tag.v