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[/] [or1k/] [tags/] [rel_29/] [or1200/] [rtl/] [verilog/] [or1200_spram_64x24.v] - Rev 1780

Rev	Log message	Author	Age	Path
1765		root	5622d 21h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_spram_64x24.v
1340	This commit was manufactured by cvs2svn to create tag 'rel_29'.		7140d 09h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_spram_64x24.v
1291	Changed behavior of the simulation generic models	lampret	7359d 01h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_spram_64x24.v
1267	Merged branch_qmem into main tree.	lampret	7423d 11h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_spram_64x24.v
1200	mbist signals updated according to newest convention	markom	7594d 12h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_spram_64x24.v
1184	Scan signals mess fixed.	simons	7653d 03h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_spram_64x24.v
1179	BIST interface added for Artisan memory instances.	simons	7661d 06h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_spram_64x24.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7787d 18h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_spram_64x24.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7959d 00h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_spram_64x24.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8246d 11h	/or1k/tags/rel_29/or1200/rtl/verilog/or1200_spram_64x24.v