URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [rel_3/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5590d 13h	/or1k/tags/rel_3/or1200/rtl/verilog/or1200_sprs.v
995	This commit was manufactured by cvs2svn to create tag 'rel_3'.		7983d 09h	/or1k/tags/rel_3/or1200/rtl/verilog/or1200_sprs.v
788	Some of the warnings fixed.	lampret	8128d 20h	/or1k/tags/rel_3/or1200/rtl/verilog/or1200_sprs.v
736	Changed generation of SPR address. Now it is ORed from base and offset instead of a sum.	lampret	8147d 10h	/or1k/tags/rel_3/or1200/rtl/verilog/or1200_sprs.v
636	Fixed combinational loops.	lampret	8184d 16h	/or1k/tags/rel_3/or1200/rtl/verilog/or1200_sprs.v
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8194d 04h	/or1k/tags/rel_3/or1200/rtl/verilog/or1200_sprs.v
596	SR[TEE] should be zero after reset.	lampret	8198d 02h	/or1k/tags/rel_3/or1200/rtl/verilog/or1200_sprs.v
589	No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.	lampret	8199d 04h	/or1k/tags/rel_3/or1200/rtl/verilog/or1200_sprs.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8214d 03h	/or1k/tags/rel_3/or1200/rtl/verilog/or1200_sprs.v