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[/] [or1k/] [tags/] [rel_4/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1781

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1765 root 5620d 13h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
1012 This commit was manufactured by cvs2svn to create tag 'rel_4'. 8007d 10h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8013d 10h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
984 Disable SB until it is tested lampret 8016d 14h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
977 Added store buffer. lampret 8016d 16h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8020d 06h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8023d 06h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8051d 14h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
870 Added defines for enabling generic FF based memory macro for register file. lampret 8087d 19h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8158d 19h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
788 Some of the warnings fixed. lampret 8158d 21h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8159d 16h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
776 Updated defines. lampret 8159d 17h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
737 Added alternative for critical path in DU. lampret 8174d 11h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
735 Fixed async loop. Changed multiplier type for ASIC. lampret 8177d 10h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8205d 07h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
636 Fixed combinational loops. lampret 8214d 16h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8227d 22h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8229d 04h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v
569 Default ASIC configuration does not sample WB inputs. lampret 8233d 02h /or1k/tags/rel_4/or1200/rtl/verilog/or1200_defines.v

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