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[/] [or1k/] [tags/] [rel_5/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1765

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1765 root 5624d 06h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
1056 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7992d 02h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
1055 Removed obsolete comment. lampret 7992d 02h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
1035 Added optional l.div/l.divu insns. By default they are disabled. lampret 7999d 23h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
1033 If SR[CY] implemented with OR1200_IMPL_ADDC enabled, l.add/l.addi also set SR[CY]. lampret 8000d 10h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 8000d 23h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
1023 Now most of the configuration registers are updatded automatically based on defines in or1200_defines.v. lampret 8004d 04h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
1022 As per Taylor Su suggestion all case blocks are full case by default and optionally (OR1200_CASE_DEFAULT) can be disabled to increase clock frequncy. lampret 8004d 06h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8017d 03h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
984 Disable SB until it is tested lampret 8020d 07h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
977 Added store buffer. lampret 8020d 09h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
962 Fixed Xilinx trace buffer address. REported by Taylor Su. lampret 8023d 23h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
944 Added OR1200_WB_RETRY. Moved WB registered outsputs / samples inputs into lower section. lampret 8026d 23h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
895 Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized. lampret 8055d 07h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
870 Added defines for enabling generic FF based memory macro for register file. lampret 8091d 13h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
790 Changed comment about synopsys to _synopsys_ because synthesis was complaining about unknown directives lampret 8162d 13h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
788 Some of the warnings fixed. lampret 8162d 14h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
778 Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs. lampret 8163d 10h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
776 Updated defines. lampret 8163d 10h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v
737 Added alternative for critical path in DU. lampret 8178d 04h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_defines.v

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