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[/] [or1k/] [tags/] [rel_5/] [or1200/] [rtl/] [verilog/] [or1200_sprs.v] - Rev 1765

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1765 root 5599d 19h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_sprs.v
1056 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7967d 15h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_sprs.v
1032 Added optional SR[CY]. Added define to enable additional (compare) flag modifiers. Defines are OR1200_IMPL_ADDC and OR1200_ADDITIONAL_FLAG_MODIFIERS. lampret 7976d 12h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_sprs.v
1011 Removed some commented RTL. Fixed SR/ESR flag bug. lampret 7986d 16h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_sprs.v
788 Some of the warnings fixed. lampret 8138d 03h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_sprs.v
736 Changed generation of SPR address. Now it is ORed from base and offset instead of a sum. lampret 8156d 16h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_sprs.v
636 Fixed combinational loops. lampret 8193d 22h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_sprs.v
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8203d 10h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_sprs.v
596 SR[TEE] should be zero after reset. lampret 8207d 08h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_sprs.v
589 No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC. lampret 8208d 10h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_sprs.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8223d 10h /or1k/tags/rel_5/or1200/rtl/verilog/or1200_sprs.v

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