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[/] [or1k/] [tags/] [stable_0_1_0/] [or1ksim/] [cache/] [icache_model.h] - Rev 1780

Rev	Log message	Author	Age	Path
1765		root	5586d 04h	/or1k/tags/stable_0_1_0/or1ksim/cache/icache_model.h
1357	This commit was manufactured by cvs2svn to create tag 'stable_0_1_0'.		7074d 17h	/or1k/tags/stable_0_1_0/or1ksim/cache/icache_model.h
1356	This commit was manufactured by cvs2svn to create branch 'stable_0_1_x'.		7074d 17h	/or1k/tags/stable_0_1_0/or1ksim/cache/icache_model.h
1350	Mark a simulated cpu address as such, by introducing the new oraddr_t type	nogj	7076d 09h	/or1k/tags/stable_0_1_0/or1ksim/cache/icache_model.h
1308	Gyorgy Jeney: extensive cleanup	phoenix	7281d 04h	/or1k/tags/stable_0_1_0/or1ksim/cache/icache_model.h
631	Real cache access is simulated now.	simons	8183d 05h	/or1k/tags/stable_0_1_0/or1ksim/cache/icache_model.h
429	cache configuration added	markom	8232d 12h	/or1k/tags/stable_0_1_0/or1ksim/cache/icache_model.h
102	Major update to include PM, PIC, Cache Mngmnt and non-interactive mode.	lampret	8439d 22h	/or1k/tags/stable_0_1_0/or1ksim/cache/icache_model.h
76	regular update	lampret	8639d 20h	/or1k/tags/stable_0_1_0/or1ksim/cache/icache_model.h
5	Data and instruction cache simulation added.	lampret	8881d 06h	/or1k/tags/stable_0_1_0/or1ksim/cache/icache_model.h