OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0/] [or1ksim/] [cpu/] [or1k/] [sprs.h] - Rev 1778

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5589d 18h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
1647 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0'. 6736d 21h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
1646 This commit was manufactured by cvs2svn to create branch 'stable_0_2_x'. 6736d 21h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
1532 Add pretty spr dumping code nogj 6937d 21h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
1508 Remove m{f,t}spr calls where we can access the spr directly nogj 6939d 05h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
1506 * Remove very slow {set,test}sprbit{,s} functions.
* Remove uses of getsprbits in time critical functions.		 nogj 6939d 05h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
1442 Replace some problematic calles to mfspr/mtspr with direct access to the spr nogj 7030d 01h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
1432 Collect most of the cpu state variables in a structure (cpu_state) nogj 7030d 01h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
1354 typing fixes phoenix 7079d 02h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7079d 23h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
997 PRINTF should be used instead of printf; command redirection repaired markom 7981d 08h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
728 tick timer works with scheduler markom 8150d 06h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
644 Modified logging of SPR accesses. Logging only explicit instruction accesses. ivang 8181d 03h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
624 Added logging of writes/read to/from SPR registers. ivang 8188d 00h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8196d 18h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
518 some more performance optimizations markom 8212d 02h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
517 some performance optimizations markom 8212d 03h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
479 connection with gdb repaired; temp_except_delay removed; lot of except and debug code cleaned; sys 203 causes stall under gdb; non-sim memory area log bug fixed markom 8228d 02h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed		 markom 8361d 03h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h
123 Bugs fixed:
- l.rfe temporarly disables exceptions
- l.sys does PC -= 4
- breakpoints now supported at peripheria locations
- uart0.rt/.tx nonexistent file segment fault

Other modifications:
- replaced string names to instruction indexes
- execute.c executes specified (in ISA table) function
- modified ISA table - flag needed for gdb
- added or32.c, which supports or32.h
- added new instructions l.mac, l.msb, l.maci, l.macrc
and their executing functions (opcodes to be revisited)
- added header acconfig.h
- modified configuration files		 markom 8418d 03h /or1k/tags/stable_0_2_0/or1ksim/cpu/or1k/sprs.h

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.