OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0/] [or1ksim/] [peripheral/] [ethernet_i.h] - Rev 1778

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5587d 18h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
1647 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0'. 6734d 21h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
1646 This commit was manufactured by cvs2svn to create branch 'stable_0_2_x'. 6734d 21h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
1461 Add an optional `enabled' paramter to every peripheral nogj 7028d 01h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
1372 Cleanup ethernet peripheral, useing the new callbacks nogj 7068d 20h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7077d 23h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
1323 Adrian Wise: or1ksim bugfix & Solaris build phoenix 7190d 01h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
1244 Added "cm" command to copy data inside memory.
Make or1ksim work on little endian platforms.
Port to Mac OS X.
Some bugfixes.
Allow JTAG write access to read-only memory regions.		 hpanther 7450d 03h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
1146 cygwin fix phoenix 7747d 14h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
889 Modified Ethernet model. ivang 8020d 23h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
867 ifdefs changed to ifs, to exclude ethernet_i header file markom 8060d 11h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
849 eth phy is now optional and disabled by default, use --enable-ethphy to enable it markom 8081d 04h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
744 Some changes and fixes. simons 8137d 21h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
702 Initial coding of ethernet simulator model finished. ivang 8156d 08h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
695 Modifications and additions for finished ethernet core. ivang 8163d 04h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
418 Renamed ethernet's RX_BD_NUM to TX_BD_NUM (following change in original files) erez 8235d 20h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
406 Renamed ethernet's RX_BD_ADR to RX_BD_NUM erez 8240d 06h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h
346 Improved Ethernet simulation erez 8261d 03h /or1k/tags/stable_0_2_0/or1ksim/peripheral/ethernet_i.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.