OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [gen_or1k_isa/] [sources/] [or32.c] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5590d 01h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1611 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc2'. 6790d 11h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1605 Execute l.ff1 instruction nogj 6798d 06h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1597 Fix parsing the destination register nogj 6810d 08h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1590 Added l.fl1 lampret 6813d 05h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1557 Fix most warnings issued by gcc4 nogj 6872d 15h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1554 fixed l.maci encoding phoenix 6890d 02h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1475 l.rfe does not have a delay slot. Don't mark it as such. nogj 7003d 05h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1452 Implement a dynamic recompiler to speed up the execution nogj 7030d 08h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1440 Reclasify l.trap and l.sys to be an exception instruction nogj 7030d 08h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1384 Fix the parameters to the l.ff1/l.maci instructions nogj 7045d 12h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7080d 06h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1346 Remove the global op structure nogj 7093d 10h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1342 * Fix generate.c to produce a execgen.c with less warnings.
* Fix the --enable-simple configure option.
nogj 7093d 10h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1341 Mark wich operand is the destination operand in the architechture definition nogj 7093d 11h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1338 l.ff1 instruction added andreje 7109d 08h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1309 removed includes phoenix 7282d 04h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7285d 01h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1295 Updated instruction set descriptions. Changed FP instructions encoding. lampret 7307d 01h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c
1286 Changed desciption of the l.cust5 insns lampret 7356d 04h /or1k/tags/stable_0_2_0_rc2/gen_or1k_isa/sources/or32.c

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.