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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cache/] [icache_model.h] - Rev 1780

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Rev	Log message	Author	Age	Path
1765		root	5595d 21h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/icache_model.h
1611	This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc2'.		6796d 06h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/icache_model.h
1486	* Seporate out the code used for handling the memory peripheral to peripheral/memory.c * Mostly decouple the memory controller from the internals of the memory handling. * Rewrite memory handling to be more linear and thus much faster. * Issue a bus error on read/write with invalid granularity.	nogj	6988d 08h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/icache_model.h
1404	Move the function of ic_clock() to mtspr() and remove it	nogj	7036d 03h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/icache_model.h
1382	Nir Mor: Implemented DCCFGR, ICCFGR, DMMUCFGR and IMMUCFGR spr registers.	nogj	7051d 07h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/icache_model.h
1350	Mark a simulated cpu address as such, by introducing the new oraddr_t type	nogj	7086d 02h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/icache_model.h
1308	Gyorgy Jeney: extensive cleanup	phoenix	7290d 20h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/icache_model.h
631	Real cache access is simulated now.	simons	8192d 21h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/icache_model.h
429	cache configuration added	markom	8242d 05h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/icache_model.h
102	Major update to include PM, PIC, Cache Mngmnt and non-interactive mode.	lampret	8449d 14h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/icache_model.h
76	regular update	lampret	8649d 12h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/icache_model.h
5	Data and instruction cache simulation added.	lampret	8890d 22h	/or1k/tags/stable_0_2_0_rc2/or1ksim/cache/icache_model.h

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