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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] [or1ksim/] [cpu/] [or1k/] [except.h] - Rev 1765

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1765 root 5660d 18h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
1611 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc2'. 6861d 03h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
1452 Implement a dynamic recompiler to speed up the execution nogj 7101d 00h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
1386 Rework exception handling nogj 7107d 04h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7150d 23h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
599 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8267d 18h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
479 connection with gdb repaired; temp_except_delay removed; lot of except and debug code cleaned; sys 203 causes stall under gdb; non-sim memory area log bug fixed markom 8299d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
437 When lsu instruction produce exception registers are preserved. simons 8306d 02h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
261 modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc markom 8346d 06h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
137 Added TRAP exception chris 8480d 07h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8514d 11h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
99 *** empty log message *** lampret 8529d 12h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
77 Regular update. lampret 8714d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
64 SPR bit definition moved to spr_defs.h. lampret 8733d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
54 Regular maintenance. lampret 8784d 09h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
49 Changed simulation mode to non-virtual (real). lampret 8845d 05h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
38 Virtual machine at the moment. lampret 8856d 16h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h
33 Handling of or1k exceptions. lampret 8860d 15h /or1k/tags/stable_0_2_0_rc2/or1ksim/cpu/or1k/except.h

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