OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [bpb/] [branch_predict.c] - Rev 1778

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5583d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
1648 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc3'. 6730d 22h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
1646 This commit was manufactured by cvs2svn to create branch 'stable_0_2_x'. 6730d 22h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
1358 Modularise config file parseing. Paving the way for further modularisation. nogj 7064d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7074d 00h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
1344 * Avoid doing a store in *every* instruction executed by storeing the instruction function unit in or32_opcodes nogj 7087d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
1243 Added "cm" command to copy data inside memory.
Make or1ksim work on little endian platforms.
Port to Mac OS X.
Some bugfixes.
Allow JTAG write access to read-only memory regions.		 hpanther 7446d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
997 PRINTF should be used instead of printf; command redirection repaired markom 7975d 09h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8202d 05h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
306 corrected lots of bugs markom 8263d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
264 updated cpu config section; added sim config section markom 8269d 04h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8437d 13h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
28 Adding COFF loader. lampret 8798d 17h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
26 Clean up. lampret 8814d 14h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8878d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
3 This commit was generated by cvs2svn to compensate for changes in r2, which
included commits to RCS files with non-trunk default branches.		 cvs 9004d 14h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c
2 First import. cvs 9004d 14h /or1k/tags/stable_0_2_0_rc3/or1ksim/bpb/branch_predict.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.