OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc3/] [or1ksim/] [cuc/] [memory.c] - Rev 1765

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5595d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
1648 This commit was manufactured by cvs2svn to create tag 'stable_0_2_0_rc3'. 6742d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
1646 This commit was manufactured by cvs2svn to create branch 'stable_0_2_x'. 6742d 11h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
1350 Mark a simulated cpu address as such, by introducing the new oraddr_t type nogj 7085d 13h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
1308 Gyorgy Jeney: extensive cleanup phoenix 7290d 08h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
997 PRINTF should be used instead of printf; command redirection repaired markom 7986d 22h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
973 generated cuc top scheduler builds without syntax errors; not tested yet markom 7993d 17h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
954 some debugging code cleanup markom 7997d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
953 burst detection for bytes & halfwords added markom 7997d 20h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
941 memory optimizations moved into main optimization loop markom 8000d 19h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
937 added file; cleanup markom 8001d 23h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
907 function calling generation; not tested yet markom 8016d 17h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
904 duplicated memory loads (same location) can be removed markom 8017d 21h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
897 improved CUC GUI; pre/unroll bugs fixed markom 8023d 14h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c
879 Initial version of OpenRISC Custom Unit Compiler added markom 8036d 14h /or1k/tags/stable_0_2_0_rc3/or1ksim/cuc/memory.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.