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[/] [or1k/] [tags/] [tn_m001/] [or1ksim/] [cache/] [dcache_model.c] - Rev 1778

Rev	Log message	Author	Age	Path
1765		root	5586d 07h	/or1k/tags/tn_m001/or1ksim/cache/dcache_model.c
861	This commit was manufactured by cvs2svn to create tag 'tn_m001'.		8069d 08h	/or1k/tags/tn_m001/or1ksim/cache/dcache_model.c
638	TLBTR CI bit is now working properly.	simons	8180d 09h	/or1k/tags/tn_m001/or1ksim/cache/dcache_model.c
631	Real cache access is simulated now.	simons	8183d 08h	/or1k/tags/tn_m001/or1ksim/cache/dcache_model.c
541	lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES!	markom	8204d 17h	/or1k/tags/tn_m001/or1ksim/cache/dcache_model.c
428	cache configuration added	markom	8232d 15h	/or1k/tags/tn_m001/or1ksim/cache/dcache_model.c
261	modified memory accesses; added cfg script; added pic test basic entry of vga; some extensions to mc	markom	8271d 20h	/or1k/tags/tn_m001/or1ksim/cache/dcache_model.c
167	- SPR values corrected - testbenches now work - lot of optimizations, use --disable-debugmod for optimal performance - some tick timer bugs fixed	markom	8357d 16h	/or1k/tags/tn_m001/or1ksim/cache/dcache_model.c
102	Major update to include PM, PIC, Cache Mngmnt and non-interactive mode.	lampret	8440d 01h	/or1k/tags/tn_m001/or1ksim/cache/dcache_model.c
54	Regular maintenance.	lampret	8709d 23h	/or1k/tags/tn_m001/or1ksim/cache/dcache_model.c
26	Clean up.	lampret	8817d 02h	/or1k/tags/tn_m001/or1ksim/cache/dcache_model.c
5	Data and instruction cache simulation added.	lampret	8881d 09h	/or1k/tags/tn_m001/or1ksim/cache/dcache_model.c