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[/] [or1k/] [tags/] [tn_m001/] [or1ksim/] [mmu/] [dmmu.c] - Rev 1782

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1765 root 5645d 21h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
861 This commit was manufactured by cvs2svn to create tag 'tn_m001'. 8128d 21h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
638 TLBTR CI bit is now working properly. simons 8239d 23h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8252d 21h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
572 Some new bugs fixed. simons 8257d 23h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
541 lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES! markom 8264d 07h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
535 stats is updated; statical single stats removed; t command output cleaned, added time output; cycles is moved to instructions; cycles now count time markom 8265d 05h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
456 Page size bug fixed. simons 8289d 01h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
438 ITLB -> DTLB lapsus fixed. simons 8291d 06h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
430 dpfault and ipfault exceptions implemented markom 8292d 05h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
429 cache configuration added markom 8292d 05h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
425 immu and dmmu configurations added markom 8292d 07h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
344 added acv test for uart; sim debug now has verbose levels; lot of bugs fixed in uart model markom 8319d 08h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
167 - SPR values corrected
- testbenches now work
- lot of optimizations, use --disable-debugmod for optimal performance
- some tick timer bugs fixed		 markom 8417d 05h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
102 Major update to include PM, PIC, Cache Mngmnt and non-interactive mode. lampret 8499d 15h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
73 Fixed all bugs. Now more or less works. IMMU still has some problems (exception start). lampret 8706d 12h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
62 OR1K DMMU model. lampret 8718d 12h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c
6 Just a regular update with exception of cache simulation. MMU simulation still under development. lampret 8940d 22h /or1k/tags/tn_m001/or1ksim/mmu/dmmu.c

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