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[/] [or1k/] [tags/] [tn_m001/] [or1ksim/] [testbench/] [cache.cfg] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5628d 07h	/or1k/tags/tn_m001/or1ksim/testbench/cache.cfg
861	This commit was manufactured by cvs2svn to create tag 'tn_m001'.		8111d 07h	/or1k/tags/tn_m001/or1ksim/testbench/cache.cfg
690	update	markom	8203d 22h	/or1k/tags/tn_m001/or1ksim/testbench/cache.cfg
631	Real cache access is simulated now.	simons	8225d 07h	/or1k/tags/tn_m001/or1ksim/testbench/cache.cfg
621	Cache test works on hardware.	simons	8226d 19h	/or1k/tags/tn_m001/or1ksim/testbench/cache.cfg
574	fixed some tests to work	markom	8239d 20h	/or1k/tags/tn_m001/or1ksim/testbench/cache.cfg
551	fsim runs 4 times faster than sim	markom	8245d 15h	/or1k/tags/tn_m001/or1ksim/testbench/cache.cfg
541	lot of new parameters concerning memory delays added; bpb parameter moved from cpu to new bpb section; UPDATE YOUR .CFG FILES!	markom	8246d 17h	/or1k/tags/tn_m001/or1ksim/testbench/cache.cfg
532	removed stats 6 command, handling SLP; function profiling is supported by profiler; subroutine level parallelism is not covered yet, but should be done in profiler	markom	8247d 21h	/or1k/tags/tn_m001/or1ksim/testbench/cache.cfg
484	Changed to support execution from various addresses.	simons	8266d 10h	/or1k/tags/tn_m001/or1ksim/testbench/cache.cfg