OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_defines.v] - Rev 1778

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
1765 root 5690d 11h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1736 See OR1200_MAC_SHIFTBY in or1200_defines.v for explanation of the change. Since now no more 28 bits shift for l.macrc insns however for backward compatbility it is possible to set arbitry number of shifts. lampret 6757d 08h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1582 Added support for RAMB16 Xilinx4/Spartan3 primitives jcastillo 6928d 22h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1334 l.ff1 and l.cmov instructions added andreje 7214d 00h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1293 Non-functional changes. Coding style fixes. lampret 7426d 16h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1288 By default l.cust5 insns are disabled lampret 7456d 14h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1284 Added some l.cust5 custom instructions as example lampret 7456d 14h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1273 Add support for 512B instruction cache. simont 7487d 23h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1267 Merged branch_qmem into main tree. lampret 7491d 01h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1228 Exception prefix configuration changed to match branch_qmem configuration. simons 7572d 01h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1200 mbist signals updated according to newest convention markom 7662d 02h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1159 No functional changes. Added defines to disable implementation of multiplier/MAC lampret 7838d 10h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1155 No functional change. Only added customization for exception vectors. lampret 7841d 11h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1139 Fixed OR1200_CLKDIV_x_SUPPORTED defines. Better description. lampret 7854d 13h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1132 RFRAM defines comments updated. Altera LPM option added. lampret 7855d 08h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1104 Added optional support for WB B3 specification (xwb_cti_o, xwb_bte_o). Made xwb_cab_o optional. lampret 7975d 01h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1078 Previous check-in was done by mistake. mohor 8015d 19h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1077 Signal scanb_sen renamed to scanb_en. mohor 8015d 19h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 8026d 14h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v
1055 Removed obsolete comment. lampret 8058d 07h /or1k/trunk/or1200/rtl/verilog/or1200_defines.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.