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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Rev 1768

Rev	Log message	Author	Age	Path
1765		root	5700d 22h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
1582	Added support for RAMB16 Xilinx4/Spartan3 primitives	jcastillo	6939d 09h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
1291	Changed behavior of the simulation generic models	lampret	7437d 03h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
1267	Merged branch_qmem into main tree.	lampret	7501d 12h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7865d 20h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8240d 01h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
636	Fixed combinational loops.	lampret	8295d 01h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8304d 13h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8308d 07h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
573	Fixed module name when compiling with OR1200_XILINX_RAM32X1D	lampret	8312d 15h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8324d 13h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v