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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_dpram_32x32.v] - Rev 1781

Rev	Log message	Author	Age	Path
1765		root	5741d 14h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
1582	Added support for RAMB16 Xilinx4/Spartan3 primitives	jcastillo	6980d 01h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
1291	Changed behavior of the simulation generic models	lampret	7477d 18h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
1267	Merged branch_qmem into main tree.	lampret	7542d 04h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
1129	Added Altera LPM RAMs. Changed generic RAM output when OE inactive.	lampret	7906d 11h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
778	Added second type of Virtual Silicon two-port SRAM (for register file). Changed defines for VS STP RAMs.	lampret	8280d 17h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
636	Fixed combinational loops.	lampret	8335d 16h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
610	Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined.	lampret	8345d 04h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
597	Fixed OR1200_XILINX_RAM32X1D.	lampret	8348d 22h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
573	Fixed module name when compiling with OR1200_XILINX_RAM32X1D	lampret	8353d 06h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8365d 04h	/or1k/trunk/or1200/rtl/verilog/or1200_dpram_32x32.v