URL https://opencores.org/ocsvn/or1k/or1k/trunk

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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_ic_ram.v] - Rev 1765

Rev	Log message	Author	Age	Path
1765		root	5628d 18h	/or1k/trunk/or1200/rtl/verilog/or1200_ic_ram.v
1293	Non-functional changes. Coding style fixes.	lampret	7364d 23h	/or1k/trunk/or1200/rtl/verilog/or1200_ic_ram.v
1273	Add support for 512B instruction cache.	simont	7426d 06h	/or1k/trunk/or1200/rtl/verilog/or1200_ic_ram.v
1267	Merged branch_qmem into main tree.	lampret	7429d 08h	/or1k/trunk/or1200/rtl/verilog/or1200_ic_ram.v
1200	mbist signals updated according to newest convention	markom	7600d 09h	/or1k/trunk/or1200/rtl/verilog/or1200_ic_ram.v
1063	Added BIST scan. Special VS RAMs need to be used to implement BIST.	lampret	7964d 21h	/or1k/trunk/or1200/rtl/verilog/or1200_ic_ram.v
504	New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.	lampret	8252d 09h	/or1k/trunk/or1200/rtl/verilog/or1200_ic_ram.v