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[/] [or1k/] [trunk/] [or1200/] [rtl/] [verilog/] [or1200_immu_tlb.v] - Rev 1765

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Rev Log message Author Age Path
1765 root 5741d 15h /or1k/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
1293 Non-functional changes. Coding style fixes. lampret 7477d 20h /or1k/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
1267 Merged branch_qmem into main tree. lampret 7542d 06h /or1k/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
1200 mbist signals updated according to newest convention markom 7713d 06h /or1k/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
1079 RAMs wrong connected to the BIST scan chain. mohor 8066d 22h /or1k/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
1063 Added BIST scan. Special VS RAMs need to be used to implement BIST. lampret 8077d 18h /or1k/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
958 Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run. lampret 8142d 08h /or1k/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
660 Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr. lampret 8326d 10h /or1k/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
617 Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways. lampret 8340d 13h /or1k/trunk/or1200/rtl/verilog/or1200_immu_tlb.v
504 New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs. lampret 8365d 06h /or1k/trunk/or1200/rtl/verilog/or1200_immu_tlb.v

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